The market requires ever faster memory devices. A limit to the maximum speed at which a memory may output data read from it is determined by the relative slowness with which output buffers of these devices produce the relative logic voltage on an output node. For this reason, the switching frequency of these output stages must be the largest possible for reducing switching times.
In general, reducing the switching times of the output buffers implies large time derivative values of the current absorbed by or discharged from the load capacitance. Because of parasitic inductances that characterize the connections of the supply pads of the device and external circuits, large time derivative values of the current may degrade performances or even cause errors.
FIGS. 1a and 1b show two output buffer stages with enable circuits of the PMOS transistor MP1 of the output buffer. Enabling circuits equivalent to those represented in the figures are used for enabling the NMOS transistor MN1. To prevent abrupt current variations it is necessary to accurately control the gates of the drivers MP1 and MN1. In practice, the gate of either the transistor MP1 or MN1 to be turned on is driven with a limited voltage gradient, via a current generator, as shown in FIG. 1a, or by a RC network, as shown in FIG. 1b, such to gradually charge/discharge the gate capacitances.
In both cases, because of the low slope of the driving voltage on the gates of the transistors, a turn-on delay Td of the transistor is determined, as schematically shown in FIG. 2 for the circuit of FIG. 1a (line 1) and for the circuit of FIG. 1b (line 2). For the illustrated case of the PMOS transistor MP1, this delay is given by the time interval necessary for reaching the threshold voltage Vtp. In the case of FIG. 1a, being I the constant discharge current of the gate capacitance of the PMOS transistor MP1, the following equation holds:Td=COX·Vtp/Ibeing COX the gate capacitance of the gate of the PMOS transistor MP1. The resulting waveform of the output voltage VOUT on the capacitor CLoad is as shown in FIG. 3. When a relatively high speed of the buffer is required, the turn-on delay Td may become of the same order of magnitude of the switching time, and this is unacceptable.
The known circuit of FIG. 4 circumvents this problem by driving the gates of the driver of the output buffer stage with a voltage having a stepwise-linear waveform with different slopes: an initial steep slope for rapidly reaching the threshold of the transistors followed by an interval with a relevantly less steep slope for reducing the disturbances (noise) introduced on the supply lines.
The charge/discharge of the gate node of the transistor MP1, in this first interval, is obtained by applying a current pulse of a finite duration δT as schematically illustrated in FIG. 4. In this case,Ipre·δT=COX·Vthwith Vth and COX being parameters that depend on the fabrication process and the working temperature, it is difficult to approximate satisfactorily the above equation in all working conditions: the time interval δT could be too short, thus penalizing performances, or it could be too long, thus turning on the drivers with too steep slopes.
U.S. Pat. No. 6,141,263, of Micron Technology Inc., discloses an output driver that comprises a plurality of circuits for driving a pull-up signal of a data driver, and a control circuit that selects a completely pre-charged circuit among these circuits when the datum generated by the output driver is logically high.
Another approach is disclosed in the U.S. published patent application No. 2003/0059997, of STMicroelectronics S.r.l., wherein the circuit for driving the driver MP1 is depicted in FIG. 5. The buffer stage has a circuit for pre-setting the voltage on the gates of the drivers, to bias them at the turn-on limit voltage, in practice making the gate-source voltage of the drivers MP1 and MN1 equal to the threshold voltage Vth.
The gate of the driver MP1 is pre-charged by setting high the control phase EN. When the voltage Vin is the ground voltage GND, the gate of the transistor MP1 is set to a voltage VCC−Vd, being VCC the supply voltage and Vd the voltage drop on the nodes of the pre-setting diode MP3 biased by the current forced by the MOS MN2.
When Vin switches to VCC, the driver MN1 is rapidly set to the turn-on edge with a circuit dual of that of FIG. 5, and the gate of the transistor MP1 is gradually brought from VCC−Vd to ground. Therefore, the transistor is completely turned on and the output capacitor CLoad is charged at the voltage VCC, that represents the datum to be output.
This approach is less critical than that of FIG. 4 from the point of view of the pre-charge at the threshold voltage. Indeed, the pre-setting diode MP3 in FIG. 5 keeps the gate voltage of the transistor MP1 always at a voltage close to the threshold voltage without the need of imposing a safety interval, which by contrast is required by the circuit of FIG. 4.
Despite the fact that the buffer of FIG. 5 is not burdened by the common drawbacks, memory devices that use these circuits often have power consumption in a stand-by state that exceeds pre-established specifications that, according to design calculations, should have been satisfied.
From thorough analysis of the operation of this circuit, it has been noticed that when the transistors MP1 and MP2 are driven in a high impedance state, they are in a under-threshold conduction state, and this could explain the excessive power consumption in a stand-by state of the memory devices.
Indeed, because of the relatively large dimensions of the drivers, the current that flows through them in this state may be relevant. Moreover, this current is not completely under control when the working conditions, supply and temperature vary, thus it may even cause failures.